1. Field of the Invention
The present invention pertains to a phase and frequency detector which can be used in frequency-synthesizing in general, and especially in frequency-generating circuits radars.
2. Description of the Prior Art
In frequency synthesizers in general, and in phase-lock loops, the element that detects the phase and frequency error is a logic device. In the current state of the art, phase and frequency detectors are of the type known under the reference MC 4344 (TTL technology) or MC 12040 (ECL technology from MOTOROLA) or again, 54 HC 4046 (CMOS or HCMOS technology) from NATIONAL SEMI-CONDUCTOR.
The principle of all these detectors is identical, and they have the same sequence chart which can be seen in FIG. 1 which depicts the analog signal VS=f(.phi.), obtained after decoding and filtering of the output logic signals from the logic device.
This phase characteristic VS=f(.phi.) is linear from -Vo to +Vo when the relative phase shift of the input signals R and V of the detector ranges between -2.pi. and +2.pi..
When the relative phase shift is greater than 2.pi., a phase-lock loop using a detector of this type is broken off but, nonetheless, the detector gives saw-toothed signals at a frequency equal to the difference between the input frequencies FR-FV, for which the mean value by the loop filter is .+-.Vo/2 according to the sign of the frequency difference. Thus the loop is frequency-aligned with a slope dF/dt=w.sub.n.sup.2 /2 where w.sub.n is the inherent locking angular frequency.
In a phase loop with an inherent angular frequency of w.sub.n and with a switch-off angular frequency of w.sub.c using a detector of this type, if the reference frequency (R) is made to vary in steps of ".DELTA.F", the loop remains locked on in phase, at a range equal to its capturing band w.sub.c, and if .DELTA.F&gt;w.sub.c, the loop is frequency-aligned with a slope equal to w.sub.n.sup.2 up to a frequency equal to FR-w.sub.c where it is phase-locked. The total frequency-alignment time is therefore all the greater as w.sub.n and w.sub.c are small, which is often the case, especially for reasons of spectral purity where band of the loop w.sub.c is deliberately limited.
Should variation of the input frequency no longer stepwise but linear, the maximum slope that the loop can follow while remaining phase-locked is dF/dt.sub.max =w.sub.n.sup.2.
3. Summary of the Invention
The phase and frequency detector, which is the object of the present invention, can be used to deliver, after decoding and filtering, a linear voltage of the differential phase of the inputs not at .+-.2.pi. but in a range of .+-.2(K+1).pi., it being possible for K to be as great as possible without any loss of frequency performance frequency for a given technology.
With a detector of this type, since the phase error is no longer limited to .+-.2.pi. but to .+-.2(K+1).pi., the phase-lock loop remains locked in phase at a frequency level (K+1)w.sub.c and if the frequency level .DELTA.F is greater than (K+1)w.sub.c, the frequency-alignment slope becomes (2K+1)w.sub.n.sup.2 /2, without modifying the pass band of the locking in.
In particular, it can be seen that if it is sought to keep the phase loop locked in phase at a frequency level .DELTA.F, it is enough for the factor K to have a value of k&gt;.DELTA.F/w.sub.c -1.
In the same way, the maximum slope that the loop can support while remaining locked in phase is dF/dt.sub.max =(K+1)w.sub.n.sup.2.
Furthermore, should the pass band of the phase loop be deliberately low, it is possible to assign, to the outputs of the stages with the rank K&gt;1, a gain .alpha. which is also greater than 1, leading to an even greater range of performances.
The detector, which is the object of the invention, can thus be used to give low pass band phase loops very great agility, without greatly penalizing the noise performances or input frequency performances.
Depending on the analog decoding selected, a detector of this type can be applied to all existing phase loops, by multiplying their dynamic performances by an extremely high coefficient.
According to the invention, a phase and frequency detector, receiving two logic input signals, R and V, essentially comprises a set of 2k+2 memory cells (MU.sub.k to MU.sub.0, and MD.sub.0 to MD.sub.k) which are cascade connected and linked in twos by 2k-1 control cells (CUD.sub.0, CU.sub.01 to CU.sub.k-1,k, CD.sub.01 to CD.sub.k-1,k) capable firstly, of transferring the information, contained in the changes of state of the signals R and V, from the end memory cells (MU.sub.k, MD.sub.k) to which they are respectively applied, and by each direction respectively, up to a memory cell MU.sub.n or MD.sub.n (depending on whether the signal R is in advance or is delayed with respect to the signal V), this memory cell then providing square waves, the duty factor of which is proportionate to the instantaneous phase shift .DELTA..phi. between the signals R and V, when (2.pi.-1)n&lt;.vertline..DELTA..phi..vertline.&lt;2n.pi., and secondly, of keeping the memory cells MU.sub.n+1 to MU.sub.k and MD.sub.0 to MD.sub.k in their initial logic state, and cells MU.sub.0 to MU.sub.n-1 in an opposite logic state, or memory cells MD.sub.n+1 to MD.sub.k and MU.sub.0 to MU.sub.k in their initial logic state, and cells MD.sub.0 to MD.sub.n-1 in an opposite logic state depending on whether the signal R is ahead or delayed with respect to the signal V.